Self timed high speed 8-bit SAR ADC in 0.35μm

This paper describes a 8-bit 22.5 MS/s Asynchronous Analog to Digital Converter (A-ADC) employing a Successive Approximation Register (SAR) architecture. The proposed system relies on single rail encoded handshaking signals to transfer data between functional blocks and perpetuates its conversion cyclically without an external clock. The components of the design are self-timed by employing completion detection techniques and takes about the same silicon area as an equivalent synchronous implementation. Due to the asynchronous operation the system's sampling rate goes up twofold, as the timing constraints are dynamically generated. The FoM of the ADC is 1.77 pj/conversion-step.