PD/sup 3/, a low-noise precise timing analog front-end integrated circuit

An analog CMOS integrated circuit (IC) for low-noise, precise timing (peak detector double discriminator) has been developed. The IC processes signals detected by a double sided microstrip detector used in the 9-18 keV energy range. The timing information is provided by a novel architecture based on a double discriminator. The leading edge of the output pulse is determined by a fixed threshold discriminator while timing information is provided by a zero crossing discriminator able to detect the maximum of the shaped signal that corresponds to the trailing edge. The PD/sup 3/ is a 64 channel front-end IC designed to be part of the MEDIM experiment, whose aim is to build a system suitable for digital mammography based on a silicon microstrip detector. Low-noise was achieved by using HP 1.2 /spl mu/m technology and optimizing the cascaded integrator with the 3.4 pF detector capacitance. In this paper we will describe the overall topology of the PD/sup 3/ and analyze the main goals of the IC which are low-noise and good timing information. In the third section circuit performance is presented, including noise and time walk measurements. The last section will present some concluding remarks on timings achievable with low-noise front-end circuits.