A 600 MHz CMOS PLL microprocessor clock generator with a 1.2 GHz VCO

A clock multiplier for the 600 MHz 72 W (estimated) CMOS Alpha microprocessor is presented. The supply voltage of the analog part of the PLL (VDDA) is provided by an on-chip voltage regulator with a decoupling capacitance. The 3.3 V supply is used to generate the quieter internal supply voltage needed for the sensitive analog part of the PLL and allows the regulator to operate properly even if the 3.3 V supply is noisy. A bandgap voltage reference is used to generate an internal reference for the supply voltage of 2.2 V. The regulator PSRR is always larger than 20 dB in the frequency range of the power supply noise, reducing the noise amplitude on the analog-supply voltage. The minimum measured supply voltage for the regulator is 2.5 V with a regulated output of 2.2 V (without noise generator).