Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT< 0.5 nm), D
it
as low as 8.0×10
¹¹
(cm
⁻²
eV
⁻¹
) and thermal stability up to 600°C is demonstrated by using La
2
O
3
as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.