Efficient motion compensation solution for H264 ultra HD codec

This Motion Compensation needs significant amount of computation in advanced video standards like MPEG4, AVS, VP8, VC-1 and H264. To understand the complexity involved in motion compensation, we categorize the Motion-Compensation (MC) into following steps. Initial step involves obtaining/computing the information needed for reference region transfer, using macro-block header data. Our solution additionally computes the reference region transfer parameters such that it is optimized for DDR memory Band-Width (BW). Hence the initial step becomes complex & computation intensive if any DDR BW optimizing algorithms to be used. The algorithm that we used is “optimal DDR BW algorithm” wherein it considers the overlap of reference regions and minimizes the total data fetch. The next step involves programming the DMA & transferring the reference region from external memory to internal memory, using the information that's been populated in the initial step. The last step of MC involves FIR filtering for sub-sample computation. Algorithms have been well developed for the motion compensation on DSP+DMA based systems. Even with interpolation friendly DSP based systems, the execution cycles needed motion compensation are well above 1500 cycles and very much close to 2000 cycles. Here in this paper, we propose a solution with consideration of a simple system to achieve the motion compensation task well below 1000 cycles. Considering the MC task split into above mentioned three tasks, the first two tasks of MC seem less cycle intensive, but it is difficult to achieve them in very low cycle budget.