Recent advances in die stacking and 3D FPGA

Die stacking technology with high-bandwidth interconnect is enabling new product architectures and capabilities. Although 3D integration, where TSVs are incorporated in active device layers, is the Holy-Grail of die stacking, the early phase of technology adoption is driven by passive silicon interposer (2.5D) based integration scheme or some variants of it. This presentation will provide an overview of recent advances in die stacking and FPGA application trends which are driving the need for stacking technologies. I will present some of the industry challenges in technology integration and design infrastructure and how they are being addressed to enable broader technology adoption.