A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation

Power supply scaling is one the most common and efficient approaches for achieving low-power operation, as both static and dynamic power consumption are aggressively reduced. Ultra-low power systems are often targeted at low-voltage operation, near or below the device threshold voltage (V_T). However, the design of such systems must overcome the inherent reduction of noise margins associated with lowering the supply, and in particular, the depleted noise margins of standard SRAM circuits. The two-port 8T SRAM bitcell has been a popular choice for the implementation of low-voltage embedded memories, due to its decoupled read buffer that solves much of the read margin limitation of the standard 6T SRAM cell [1]. However, the 8T circuit is still limited by write margin, and in addition, does not support half-select operations, which are a requirement of many systems. Another disadvantage of the 6T and 8T circuits is that in standby, they present several transistors with relatively high leakage paths through them, leading to significant static power dissipation. In this paper, we propose a novel Double-Feedback SRAM (DF-SRAM) bitcell with improved write margins for low-voltage operation, reduced leakage for ultra-low power consumption, and improved half-select support.