Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding

We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200 °C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.