Low complexity FPGA implementation of Register Exchange Based Viterbi decoder

Viterbi decoders are either implemented as a Trace Back model or Register Exchange model. The trace back model is more popular, despite having large latency, because it requires less power and has less hardware complexity. In this paper a low complexity FPGA implementation of Register Exchange method is presented which gave the same error performance as that of trace back method at the same time having less hardware requirement. This is achieved using continuous decoding that normalises the state metric for every symbol processed, which reduces the size of registers used for storing the state metric. Split search that finds the best path every clock cycle was used for the normalisation and choosing the data output. This makes it possible to have output rate of one (1) symbol which reduces the number of registers required to save the path history bits to be outputted and reduces delay. Result of implementation of rate half codes of constraint length 7 and generator vector [1111001, 1011011] shows that for the same performance, the Register Exchange implementation presented, used no RAM as in the case of normal trace back and one-pointer algorithm. It requires less silicon area (5.5% less FPGA slices). It can run as fast as or even faster than the latter implementations and has less latency (1-decoding depth as compared to 4-decoding depth of trace back method) than the rest.