Passive inductors in silicon: A design proposal

This paper present the induction phenomenon in planar inductors built with integrated circuit (IC) technology, and their analytical model description based on Greenhouse proposal, which not only incorporates the impact of no idealities of the substrate, but those parameters under the designer control, that are the support of every planar inductor design. To validate the design proposal, experimental results of a square inductor are presented, built with standard CMOS 5 volts, N Well, 0.5 micrometers process. The maximum relative error between the measured value, the simulated one, and the analytical one is more or less 4.5 percent.