Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45
^°
and -0.25
^°
, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.