A novel 10bit 90MS/s 2b/cycle SAR ADC

A 10-bit 90MS/s Successive Approximation Register (SAR) analog-to-digital converter (ADC) is realized in TSMC 0.18μm CMOS process. With 2b/cycle technique and new proposed asynchronous control logic, the proposed SAR ADC achieves rapid conversion rate, low power, leading to SNDR of 55.3 and SFDR of 64.7 at 90MS/s with 43M input. The active area with the digital calibration is 0.6×0.8mm
²
.