A current-mode FIR-filter-based receiver front-end for blocker filtering

A digital RF receiver front-end employing a FIR(Finite Impulse Response) filter is proposed for SAW-less receiver architecture, where the large out-of-band interferer can be rejected selectively by using a scalable frequency response property of FIR filter. The FIR filter, followed by the transconductor stage and current-commutating passive mixer, operates in current domain to improve the linearity. Also, the clock generator circuit can be simplified by making the FIR filter operate with 8-phase clock signal. The designed receiver front-end is fabricated using UMC 0.13 μm CMOS process. The chip shows unwanted blocker rejection over 80 dB, with good linearity of +3.94 dB IIP
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