Mobility enhanced power CMOS

This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art R
_SP
performance. By realizing <;100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, I
_DSAT
and I
_DLIN
increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.