High-density chain ferroelectric random access memory (chain FRAM)

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F/sup 2/ size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V/sub dd/ cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation.