A High Power-Efficiency D-Band Frequency Tripler MMIC With Gain Up to 7 dB

A novel frequency tripler consisting of a harmonics generating stage and a converting stage is proposed. A common-emitter transistor in the first stage is used to produce mainly the first to third harmonics, while, a common-emitter transistor in the second stage converts simultaneously the first and the second harmonics into the third harmonic, and also amplifies the third harmonic at the input. The third harmonics obtained from different mechanisms add in favorably phase, and consequently improving the tripler's conversion gain. A proof-of-concept circuit is designed and manufactured in a 0.25 μm InP DHBT Technology. The tripler has a conversion gain between 0 dB to 7 dB in the output frequency range from 110 to 155 GHz. It demonstrates also up to 30 dBc rejection ratio of the undesired first, the second and the fourth harmonics. The tripler consumes a dc power of only 45 mW, and achieves a state-of-the-art peak power efficiency of 20.2%, which to the authors' knowledge, is the highest obtained among triplers with positive gain published so far.