SMC: A Shared Memory Based SpaceWire Controller Solution

Nowadays, as an emerging international standard, the SpaceWire buses become more and more popular in space applications, especially in the On Board Computer Systems. However, since most space CPUs have not integrated on-chip SpaceWire Controllers, it is important to design efficient SpaceWire Controllers with the assistance of external FPGA chips. As the speed of SpaceWire bus exceeds hundreds of Mbps, the SpaceWire Controller requires plenty of memory resources to send and receive packages. Nevertheless, the storage resources of radiation-tolerant space FPGA are severely constrained, especially for the commonly used antifuse FPGA families, i.e., actel RTAX series. Therefore, it is very critical and challenging to design a SpaceWire bus controller with few on-chip memory resource requirements. In this paper, we propose a novel design, SMC (Shared Memory based spacewire Controller). In SMC, the FPGA chip which implements the SpaceWire Controller is connected to the CPU memory buses, while the Shared Memory Chip, which contains the reading and writing FIFOs, is connected to the FPGA and shared by SpaceWire Controller and CPU. We carefully design the sub-modules of the SMC model, including the CPU interface module, SpaceWire transceiver module, flow control module and SRAM arbitration access module, etc.. To enhance the system performance, we design an efficient interrupt-based packet sending and receiving mechanism. We implement the SMC logic within an Actel A3P1000 FPGA, and evaluate its performance in a practical OBC platform. Experimental results show that, our SMC design can effectively reduce the memory requirements of SpaceWire controllers, and provides an effective solution to implement SpaceWire Controller of CPU based on FPGA.