A new processor architecture exploiting ILP with a reduced instruction word

Explores a parallel processor keeping low hardware complexity while reducing the size of the instruction word. This is obtained by using an indirect instruction coding: the most frequently executed instructions are first stored in an Instruction Register File (IRF) so that the address in the IRF can then be fetched instead of the entire instruction word. It will allow to develop a VLIW-based processor applicable to low-cost systems where caches are reduced or eliminated by interfacing it with high-speed RAMs such as Rambus or SLDRAM. The Indirect RISC (IRISC) architecture is presented. It is a 64-bit fixed-point processor with eight identical parallel processing units. Each processing unit is a standard RISC processor supporting an instruction set close to DLX. It can also feature conditional instructions. Like the VLIW architecture, the detection of the instruction parallelism is handled by the compiler. There are two register files: the Instruction Register File (IRF) that stores the 128 most frequently executed instructions, introducing a supplementary pipeline level compared to a traditional RISC processor, and the Data Register File (DRF) containing 8 sets of 16 general-purpose registers, each addressable by all the processing units.