Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC sample clock synthesis

This paper presents a design technique for generation of GHz ADC sampling clock phases from a low-cost low-frequency clock source. Jitter of order 0.1ps is enabled using a DLL-based frequency multiplication method. Nonidealities of the DLL approach are mitigated through digital background correction. Simulated results in a 180nm CMOS process are presented.