Power-aware SoC test optimization through dynamic voltage and frequency scaling

Reducing test cost by minimizing the overall test time remains one of the main goals of System-on-Chip (SoC) testing. Power-aware strategies optimize the overall test time of a SoC for a global peak power budget. Test time and test power can be regulated by V
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and test clock frequency to optimize SoC test schedules for a given power budget. Dynamic voltage and frequency scaling (DVFS) techniques have been used in the past to optimize energy efficiency in SoCs. In this paper, we extend the concept of DVFS to optimize the test scheduling of SoC. We adopt a sessionless test scheduling strategy and provide a simple heuristic approach for its optimization. The proposed idea is implemented on several ITC02 benchmarks. Results show significant test time reduction over sessionless reference test schedules for which V
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and clock frequency are fixed at nominal values.