FPGA acceleration of Markov Random Field TRW-S inference for stereo matching

In this paper, we present our hardware accelerator for inference computations on Markov Random Fields (MRFs), which wins the “adjusted run time” category of MEMOCODE 2013 design contest. The contest problem is to accelerate the popular Belief Propagation (BP) algorithm for MRF stereo matching, but BP often suffers from non-convergence in its MRF inference. To overcome the drawbacks of BP, we show how a superior method-Sequential Tree-Reweighted message passing (TRW-S)-can be rendered in hardware. TRW-S has reliable convergence, guaranteed by its so-called “sequential” computation. We show how to implement TRW-S in FPGA hardware so that it exploits significant parallelism and memory bandwidth. Our FPGA implementation demonstrates superior MRF inference performance and comparable quality of stereo matching results on the provided stereo matching tasks comYXB3-02195-A021pared to the reference BP software.