Equivalence checking for synchronous elastic circuits

Synchronous elastic circuits are clock-based latency insensitive circuits. Elastic circuits are typically synthesized from synchronous circuits. After synthesis, additional buffers can be arbitrarily inserted in the data path of an elastic circuit without altering its functionality to resolve timing issues. We have developed a verification tool that can check the equivalence of an elastic circuit (even after the inclusion of any number arbitrarily placed additional buffers) with its synchronous parent circuit. The tool inputs elastic circuits in VHDL. We have developed an algorithm that automatically computes efficient mapping functions used to map elastic circuit states with states of the synchronous parent circuit. Such mapping functions (required for equivalence checking) can be challenging to compute automatically, as the inclusion of additional buffers can drastically alter the pattern of data flow through the circuit. The capacity of the equivalence checker is demonstrated with results from 24 elastic circuit benchmarks, many of which have over 100,000 gates and 1,000 latches.