Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip

This paper presents design and implementation of a 12-GS/s fully differential data acquisition (DAQ) system-on-chip (SoC) fabricated in a standard 130-nm CMOS process. The proposed DAQ is comprised of a 4-bit flash ADC and four channels of 1:32 demultiplexer (DEMUX) with on-chip custom registers. At 12-GS/s sampling rate, the DAQ SoC achieves an SNDR of 19.2 dB for 2.9-GHz input signal and 24.2 dB for low-frequency inputs. The flash ADC and each DEMUX channel consume 200- and 260-mA from 1.3 V supply and occupy an active area of 0.85 and 0.70
${\mathrm{ mm}}^{2}$
, respectively. The DAQ SoC does not employ time interleaving and calibration techniques. In the meantime, no BW- or speed-enhancing inductors have been used in the proposed system. The DAQ prototype achieves the highest sampling rate in 130-nm CMOS technology.