FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories

High rate low density parity check (LDPC) codes that are employed in NAND flash memories are required to have excellent error correcting performance and should avoid error floors at low bit error rate. For evaluating the performance of error correcting codes FPGA based accelerators are used. This paper presents a high speed, partially parallel and flexible decoder design for evaluating the performance of regular Quasi cyclic LDPC codes. We have targeted euclidean geometry (EG) LDPC codes which have high code rate and good error correcting performance. The throughput of the decoder is increased by using a fully parallel check node processor along with the layered decoding algorithm. The proposed decoder is implemented on XILINX XC7V2000T FPGA device. Synthesis results show that the proposed decoder is 60% faster as compared to the previously published FPGA implementations and is also capable of decoding high circulant weight EG-LDPC codes.