An adaptive coherence protocol with adaptive cache for multi-core architectures

Next generation multicore processors and their applications will process massive amounts of data with significant sharing. Data movement between cores and shared cache hierarchy and its management impacts memory access latency and consumes power. The efficiency of high-performance shared-memory multicore processors depends on the design of the on-chip cache hierarchy and the coherence protocol. Current multicore cache hierarchies uses a fixed size of cache block in the cache organization and in the design of the coherence protocols. The fixed size of block in the set is basically choosen to match average spatial locality requirement across a range of applications, but it also results in wastage of bandwidth because of unnecessary coherence traffic for shared data. The additional bandwidth has a direct impact on the overall energy consumption. In this paper, we present a new adaptable and implementable cache design with novel proposal of the design of cache coherence protocol that eliminate unnecessary coherence traffic and match data movements to an applications spatial locality.