Electrical and photonic I/O test and debug

This session addresses recent test challenges associated with high-speed I/Os implemented in electrical and photonic IC forms. In addition to conventional SERDES I/O test challenges, such as transmitter jitter generation and receiver jitter tolerance type tests, stress techniques in loop-back, known-good-die (KGD), and design-validation to debug to high-volume manufacturing, this session will include a discussion about similar photonic transmitter and receiver test and debug challenges. Moreover, this session will also cover the test and debug challenges of CMOS and silicon-photonic integration, either monolithically or heterogeneous, to provide overall cost-power-density-performance trade-offs and optimizations. Issues pertaining to reliability of these systems will also be discussed.