A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC

We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumption, and small area. The prototype chip was fabricated in 65nm CMOS, achieving 0.84ps LSB, 2.47mW power consumption, and 0.06mm² area occupation. With 8-bit outputs, the DNL and INL are −0.7/1.0 LSB and −2.7/1.7 LSB, respectively.