A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

A 12-bit SAR ADC is presented with a FoM of 11.7fJ/conversion-step. The ADC employs a two-step decision DAC switching technique for improving the ADC's linearity and switching energy using smaller input capacitance. It effectively eliminates the largest capacitor-DAC middle-code transition error. The proposed switching scheme can also tolerate DAC settling errors without requiring redundant capacitors. The ADC core occupies an area of 0.079mm
²
in a 0.11μm CMOS process. At 1MS/s, it consumes 24μW from a 0.9V supply. Measured DNL and INL are 0.29LSB and 0.55LSB respectively. Measured SNDR and SFDR are 68.3dB and 82dB respectively. Measured ENOB is 11.05b at the Nyquist-rate input.