IO Standard Based Green Multiplexer Design and Implementation on FPGA

In this work, we are using Stub Series Transistor Logic (SSTL) on the simplest VLSI circuit multiplexer and analyze the power dissipation with different class. Using SSTL15 in place of SSTL2_II_DCI, there is reduction of 304mW power i.e. 76.19% power reduction. Using HSTL_I_12 in place of HSTL_III_DCI_18, there is reduction of 157mW power i.e. 62.3% power reduction. HSTL and SSTL are IO standards taken under consideration. SSTL minimum power consumption is almost same as HSTL. But, the power dissipation of SSTL is 58.73% higher than HSTL, when we consider maximum power dissipation of both. Virtex-6 is an FPGA on which we implement this low power design. Xilinx ISE 14.1 is an ISE tool to design and synthesize multiplexer.