Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities

This paper presents a fast and effective approach to cell-type selection and V
_th
assignment. In our approach, initially a solution without slew and load violation is generated. Then, the Lagrangian Relaxation considering lambda-delay sensitivities is used to reduce leakage power trying to keep the circuit without timing and load violations. If the set of cell-types given by Lagrangian Relaxation produces a circuit with negative slack, a timing recovery method is applied to find near-zero positive slack. The solution without negative slack is introduced to a power reduction step. The sizing produced using our approach could achieve up to 28% in power reduction compared to state of the art works. The leakage power of our solutions is, on average, 9.53% smaller than [1] and 12.45% smaller than [2]. Furthermore, the method is 19× faster than [1] and 1.18× faster than [2].