Evaluating CLB designs under multiple SETs in SRAM-based FPGAs

Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB design among different architectures of hardened CLBs, under the constraint of limited overheads. After synthesizing the candidate CLB architectures in STM 65nm CMOS technology, we compare them in terms of logical masking and reliability, and evaluate their area, time and power overheads. The most reliable CLB design is selected according to a metric expressing the tradeoff between the reliability gain and the cost penalties.