Experimental characterization of BTI defects

Selected physical and electrical characterization of gate-oxide defects is reviewed. Interfacial dangling bond defects at interfaces of Si and SiGe are characterized electrically and compared to the electron spin resonance data. It is found that additional silicon dangling bonds (P
_b0
-ceters) acting as amphoteric interface traps are generated upon oxygen scavenging anneal. A close density of P
_b0
centers is also found in Si/SiGe/Si/HfO
₂
stack. The Ge dangling bond defects (Ge P
_b1
centers) found at interfaces of SiGe with thermal SiO
₂
are shown to behave as acceptor centers. The properties of individual gate-oxide defects in FETs are studied with Time-Dependent Defect Spectroscopy (TDDS), an electrical characterization technique. The primary properties of a defect are its capture and emission time constants, both dependent on the local electric gate field and the temperature. Considering the wide distributions of these defect properties, complete characterization of many defects is required over the full gate and drain voltage range from 0 to VDD at different temperatures. This is desirable in order to model degradation for large, “analog” FETs and to model the ΔV
_th
-variability of deeply-scaled FETs. The impact of individual charged defects on transistor properties is then discussed. It is shown that the shift in the threshold voltage is exponentially distributed, with a small fraction of defects causing significant shifts of tens of mV. The average impact per charged defect is experimentally confirmed to be increasing with the gate oxide thickness, the substrate doping, and with the decreasing FET area. The average impact per charged defect is found to be reduced in SiGe substrates, contributing to lower degradation of SiGe-based FETs. In low-doped substrates, other sources of variability, such as interface states, are shown to take over. The impact of a single charged gate-oxide defect on the full I-V characteristic is measured and corroborated by atomistic device simulations, thus enabling the path to compact modeling of degraded deeply-scaled FET devices. Finally, the model explaining the correlation between drain and gate current RTN is discussed.