Highly robust and sensitive charge transfer sense amplifier for ultra-low voltage DRAMs

A new charge transfer sense amplifier for low voltage DRAMs is proposed. The proposed charge transfer sense amplifier has two features. One is the double boosting sensing node structure, and the other is the dynamic presensing latch. The double boosting sensing node structure consists of two boosting capacitors. The 1
^st
and 2
^nd
boosting capacitors are placed at the boosting nodes and sensing nodes, respectively. The sensing node and boosting node are connected by a PMOS diode-connected transistor. This structure is efficient in achieving high sensitivity in ultra-low supply voltage conditions. The dynamic presensing latch is placed at the sensing nodes between the bit-line pair. The sensing node voltage difference (ΔV
_SA
) develops by the operation of the dynamic presensing latch. Pull-down/up latch works effectively because ΔV
_SA
is larger than bit-line voltage difference. With a 0.5V power supply voltage using a NCSU 45nm process, the proposed charge transfer sense amplifier brings a significant increase of about 3.89 times in ΔV
_SA
and a decrease of 22.3% in the sensing delay time compared with the characteristics obtained by the best-known prior scheme.