Development Flow for FPGA-Based Scalable Reconfigurable Systems

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, for instance we can change a part of the initial functionality after its deployment, where a complete configuration is not needed, and the total area required is reduced. However, the design of partially reconfigurable systems has been a complex task yet. This work try to facilitate the design process and proposes a new development flow, which reduces mistakes during first stages of the design and makes the building of partial reconfiguration projects easier. In addition, we provide a dedicated hardware component, which manages bit streams nd dynamic areas. This component speed up the reconfiguration time, accomplishing a speed about 180MB/s.