An SCMOS digital cell family for mixed-signal applications

A CMOS digital cell family has been developed for use in VLSI mixed-signal applications. This cell family has been designed with MOSIS scaleable CMOS rules for use with triple-level metal processes and consists of cells 90 /spl lambda/ high. The cell family includes approximately 80 cells incorporating conventional logic and flip-flop functions and is designed for maze routing with automatic place and route tools, such as CELL3. This cell family is unique in that all substrate and well connections are isolated from the digital power busses, allowing significantly reduced digital noise coupling to the substrate. Demonstrations of this cell library on the MOSIS.6 micron HP process (/spl lambda/=.3 micron) are underway.