An analysis of full adder cells for low-power data oriented adders design

This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values than traditional model, based on switching activity only. Obtained results allow analyzing what structure of full adder should be used for specific data summation. So, such model and analyses can lead to developing of data oriented low power design methods. Based on energetic parameters assessed for 1-bit full adders, multi-bit adders were considered. Theirs power consumption versus summed data was analyzed.