A low-area asynchronous router for clock-less network-on-chip on a FPGA

The router is the main block of the Network-on-Chip where most of the major decisions about the route directions and sub-system communications are taken. Reducing the design area of the Network-on-Chip router is one of the most important factors that contribute for its efficiency. This paper presents a new asynchronous router design for clock less Network-on-Chip using handshaking protocol that utilizes low area on SPARTAN-3E FPGA. The simulations results show that the proposed router utilises only 3.18% of total available slices on the used FPGA. When compared with previous works, the proposed design significantly reduces the area of the design by an average of 282%. Thus, the scalability of the Network-on-Chip on the FPGA is improved. In addition, the proposed router has a new feature that will support the applications that do not require the usage of clock or where laying the clock to the different Intellectual Property Cores and the internal components of the router is not possible. Moreover, using the proposed router, it is still possible to support a maximum of five simultaneous routing requests. The simulations results of the proposed router and other designs are presented.