Collision detection VLSI processor for intelligent vehicles based on a hierarchical obstacle representation

To avoid a traffic accident, it is needed to detect a possible collision between a vehicle and obstacles at high speed. If we increase the accuracy of an obstacle representation, it results in an increase in the number of discrete points to represent obstacles and the number of collision checks for the discrete points. We propose a hierarchical collision detection algorithm to reduce the time complexity. First, collision checks with a coarse representation of obstacles are performed. If collision exists with such a representation, next, checks with a fine one are performed to detect collision. Otherwise, it is not required to perform collision checks with a fine representation. Since vehicle pixel information is predetermined and not changed, a high-performance ROM-type CAM is employed to perform a matching operation in parallel. Parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on matrix multiplications. The performance of the proposed VLSI processor is much higher than that of the equivalent special-purpose processor without using the hierarchical representation.