Simulation and implementation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron

We have been studying ultra-low-power logic circuits using adiabatic quantum-flux-parametron (AQFP) logic, whose power consumption can be decreased significantly by changing their potential energies adiabatically using AC exciting currents. In this study, we designed an 8-bit carry look-ahead adder (CLA) using an AQFP cell library based on the AIST Nb 2.5 kA/cm
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standard process (STP2) and evaluated its circuit properties. The CLA is composed of 1224 critically-dumped 50-μA Josephson junctions, which occupy the area of 1.74 × 0.99 mm
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. Simulation results show that the CLA has a wide bias margin of ±29.5%, and the energy dissipation is 16.4 aJ per clock cycle at 5-GHz operation.