Modeling and calibration of ADP process for inductance calculation with InductEx

The AIST advanced process (ADP2), with 9 Nb layers and 1 µm minimum Josephson junction size is currently the most complex low-Tc superconductive integrated circuit fabrication process in operation. With planarization for all layers below the main ground plane, and conductors that may traverse several layers, modeling inductance for numerical calculation requires special attention to the capabilities of the extraction tool. We present specific improvements made to InductEx to model the ADP process, including support for selective layer planarization, multiple ground planes and conductors below a ground plane. We discuss calibration of extracted values to experimental results, and show results for pulse transfer cells with inductive coupling and isolated ground planes.