Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiter

The Data Processing Unit (DPU) for the Polarimetric and Helioseismic Imager (PHI) instrument on the ESA Solar Orbiter mission will use Xilinx Virtex-4 XQR4VSX55 FPGAs for high data rate acquisition and processing tasks. This paper discusses the feasibility of using this type of SRAM based FPGAs for these high data rate tasks. Firstly scenarios of the radiation environment are derived from the orbit description. Then relevant radiation effects on microelectronics are recapitulated and finally the resulting error rates under various conditions are estimated. The prediction of error rates is based on estimation of upset rates which in turn is used for a prediction of system error rates. The mitigation techniques Triple Modular Redundancy (TMR) and configuration memory scrubbing reduce the system error rate to achieve predicted rates that make the construction of this system feasible. Furthermore the system set up of the DPU with a radiation hardened control processor and fixed antifuse FPGA is such, that only tasks are loaded to the Virtex-4 FPGAs, for which sporadic failures can be detected and corrected.