A modified structure for high-speed and low-overshoot comparator-based switched-capacitor integrator

In this paper, a simpler and faster comparator-based switched-capacitor (CBSC) architecture than the conventional CBSC circuits is presented. A voltage dependent current source is used to improve the performance of the CBSC integrator. Also, the preset phase is modified to increase the sampling frequency. A CBSC integrator is designed and simulated in 180 nm CMOS technology with 1.8 V supply voltage to verify this method. The input signal frequency of sinusoidal wave and the sampling frequency are 200 kHz and 10 MHz, respectively.