A study of latch-up mechanisms for adjacent pins on multiple power supply circuits

Traditional latch-up (V
DD
-to-V
SS
) in CMOS IC's is formed by the parasitic p-n-p-n structure between VDD and VSS. In modern technologies, although the guard rings and substrate/ well pickups could efficiently overcome the latch-up failure in CMOS ICs, the latch-up failure phenomenon is still existed in many special application circuits. With mixed signal design requirements, there are more than 2 kinds of devices that are deployed in one chip to implement the design with higher voltage system on the advanced technologies with lower voltage application in the mixed-voltage process. Therefore, these comprehensive process and design approaches could provide more flexibility for the chips to be connected with older system [1–2]. A latch-up phenomenon is reported here that the latch-up current path occurs between adjacent power pins of 65nm process, IO circuit is powered by different power supplies. In this product, IO circuitry is with 3.3V and core circuitry is with 1.2V power supply. Because there is no V
DD
-to-V
DD
latch-up rule, the 3.3V n-well to 1.2V n-well space was < 10 um (note: without any guard rings in between). Latch-up immunity of I/O pins resulted from a higher substrate potential required on the base-emitter junction forward bias of LQpnp.