Realization of the CMOS pulsewidth-modulation (PWM) neural network with on-chip learning

In this paper, a CMOS very large scale integration (VLSI) design of the pulsewidth-modulation (PWM) neural network with both retrieving and on-chip leaning functions is proposed. In the developed PWM neural system, the input and output signals of the neural network are represented by PWM signals whereas the multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Therefore, the designed neural network only occupies the small chip area. After compensating the nonideal effects of the switches, the designed circuits have good linearity and large dynamic range. This makes the implementation of onchip learning feasible. To demonstrate the learning capability of the realized PWM neural network, the delta learning rule is realized. An experimental chip with two neurons, twelve synapses, and the associated learning circuits has been fabricated in 0.8 /spl mu/m CMOS double-poly double-metal process. The chip area, including the pads, is 3.45 mm/spl times/3.45 mm. From the measured results, the linearity of synapses versus weight voltages and input pulsewidths can almost be kept under /spl plusmn/1% and /spl plusmn/0.2%, respectively. The measured results on the three learning examples on AND function, OR function, and simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.