Simulation of temperature cycling effects on electromigration behavior under pulsed current stress [VLSI metallization]

The temperature cycling effect on electromigration behavior under pulsed current conditions for metallization used in very large scale integrated (VLSI) devices is numerically investigated. This involves the solution of a two-dimensional (2-D) heat-conduction equation and a one-dimensional (1-D) diffusion-drift equation. We find that the characteristic thermal response time for establishing the equilibrium, for a typical VLSI metallization structure, is slightly longer than 1 ms. As a result, the steady-state temperature difference in the metal line between the upper and lower values in response to the pulsed current operation is maximized when the frequency is below 250 Hz with a duty factor of 0.5. The temperature difference decreases with increasing frequency. At frequencies above 10 MHz, the thermal capacity of the metal line inhibits appreciable temperature fluctuation. For a constant line temperature the time-dependent vacancy buildup has been shown to be proportional to /spl tau//sup m/ with m=2 (where /spl tau/ is the duty factor), consistent with the "average model" for predicting the failure time. In this study, we confirm the speculation that Joule heating due to an elevated current density employed in accelerated life testing can bring about an m<2 dependence at low frequencies. The confirmation is based upon the solution of the electromigration initial and boundary value problem by taking into account the temperature dependence of several relevant physical parameters, particularly the vacancy diffusivity.