Memory hierarchy limitations in multiple-instruction-issue processor design

Most research on multiple instruction issue processor architecture assumes a perfect memory hierarchy and concentrates on increasing the instruction issue rate of the processor. In contrast, the paper assumes an ideal processor model and seeks to quantify the limitations placed on superscalar processor performance by the memory hierarchy. The paper concludes that sustaining processor issue rates of four or more will probably ultimately require systematic preloading of cache blocks and the use of trace caches.