Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches

A spin-transfer torque MRAM with complementary polarizers, suitable for on-chip caches, is proposed in this paper. The average critical current for write in our proposed structure is lower than standard STT-MRAM, improving write-ability and reliability. Our proposed structure also has self-referencing differential read operation having subnanosecond read delay, and lower read disturb torque, improving sensing margin and disturb margin by 20%-60% and 55%-70% over standard STT-MRAM, respectively.