A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation

A versatile signal reconstruction platform designed in a 40nm CMOS process is presented. The chip supports high-dimensional sparse signal reconstruction for compressed sensing and sparse representation. A 4G entries/s (8Gbps) high-throughput sensing matrix generation engine is proposed. It r educes o ver 75% external bandwidth and 77% processing cycles. The chip achieves 401GFlops/W power efficiency with 16 multi-processing cores. The chip also yields over 1000× improvement of computing time compared to software implementations.