A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM

This paper describes DLL architecture and ZQ calibration method for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM. Proposed DLL consists of one DLL with CML DCDL and another DLL with CMOS DCDL which tracks first one for low jitter and low power characteristics. Quantization error minimized (QEM) ZQ calibration is proposed for better signal integrity and yield improvement. The implemented DLL dissipates 6.5mW from a 1.2-V supply. Output jitter is 2.99 ps
_rms
with all high data, single bank read pattern and 7.75 ps
_rms
with random data, all bank interleaved read pattern. Despite 100 times of ZQ calibration, measured mismatch between pull up and pull down (MMPuPd) over all DQs is under 2 %.