A 38% access time improvement in 40nm CMOS technology with Triple-Wire-Program-Cell scheme for high density MROM

This paper proposes a Triple-Wire-Program-Cell (TWPC) scheme and Triple-Line-Decoder (TLD) for high density MROM. TWPC consists of a cell transistor with triple wires (bit lines) and stores two-bit data in a cell. These designs have been implemented in 40nm test chips without cell array area overhead. The access time is improved by 38% with TWPC scheme in 40nm 1Mbit macro.